RSYN: A system for automated synthesis of reliable multilevel circuits K De, C Natarajan, D Nair, P Banerjee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2 (2), 186-195, 1994 | 148 | 1994 |
Synthesis of delay fault testable combinational logic K Roy, JA Abraham, K De, S Lusky 1989 IEEE International Conference on Computer-Aided Design, 418-421, 1989 | 77 | 1989 |
Failure analysis for full-scan circuits K De, A Gunda Proceedings of 1995 IEEE International Test Conference (ITC), 636-645, 1995 | 65 | 1995 |
System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code A Balakrishnan, K De, J Qian US Patent 6,135,647, 2000 | 62 | 2000 |
Defect isolation using scan-path testing and electron beam probing in multi-level high density asics GA Lindberg, S Prasad, K De, AK Gunda US Patent 5,663,967, 1997 | 62 | 1997 |
Evaluation of early failure screening methods [ASICs] T Barrette, V Bhide, K De, M Stover, E Sugasawara Digest of Papers 1996 IEEE International Workshop on IDDQ Testing, 14-17, 1996 | 49 | 1996 |
Test methodology for embedded cores which protects intellectual property K De Proceedings. 15th IEEE VLSI Test Symposium (Cat. No. 97TB100125), 2-9, 1997 | 36 | 1997 |
Accurate pre-layout estimation of standard cell characteristics H Yoshida, K De, V Boppana Proceedings of the 41st annual Design Automation Conference, 208-211, 2004 | 25 | 2004 |
ProperSYN: A portable parallel algorithm for logic synthesis K De, B Ramkumar, P Banerjee Proceedings of the 1992 IEEE/ACM international conference on Computer-aided …, 1992 | 22 | 1992 |
Test shells for protecting proprietary information in asic cores K De, S Venkatraman, A Gunda US Patent 5,903,578, 1999 | 19 | 1999 |
Protecting proprietary asic design information using boundary scan on selective inputs and outputs K De US Patent 5,638,380, 1997 | 18 | 1997 |
Parallel algorithms for logic synthesis using the MIS approach K De, LA Chandy, S Roy, S Parkes, P Banerjee Proceedings of 9th International Parallel Processing Symposium, 579-585, 1995 | 18 | 1995 |
Logic partitioning and resynthesis for testability K De, P Banerjee 1991, Proceedings. International Test Conference, 906, 1991 | 17 | 1991 |
Parallel logic synthesis using partitioning K De, P Banerjee Parallel Processing, 1994. Vol. 1. ICPP 1994. International Conference on 3 …, 1994 | 16 | 1994 |
Method and apparatus for extracting assume properties from a constrained random test-bench K De, E Cerny, P Dasgupta, B Pal, PP Chakrabarti US Patent 7,797,123, 2010 | 15 | 2010 |
Method and apparatus for extracting assume properties from a constrained random test-bench K De, E Cerny, P Dasgupta, B Pal, PP Chakrabarti US Patent 7,797,123, 2010 | 15 | 2010 |
PREST: a system for logic partitioning and resynthesis for testability K De, P Banerjee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 (4), 514-525, 1993 | 10 | 1993 |
PREST: a system for logic partitioning and resynthesis for testability K De, P Banerjee Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 1 (4), 514-525, 1993 | 10 | 1993 |
Reliability driven logic synthesis of multilevel circuits K De, C Wu, P Banerjee Circuits and Systems, 1992. ISCAS'92. Proceedings., 1992 IEEE International …, 1992 | 10 | 1992 |
A portable parallel algorithm for logic synthesis using transduction K De, B Ramkumar, P Banerjee IEEE transactions on computer-aided design of integrated circuits and …, 1994 | 9 | 1994 |