Joseph Zambreno
Joseph Zambreno
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Cited by
Cited by
Preventing integrated circuit piracy using reconfigurable logic barriers
AC Baumgarten, A Tyagi, J Zambreno
IEEE Design and Test of Computers 27, 66-75, 2010
Minebench: A benchmark suite for data mining workloads
R Narayanan, B Ozisikyilmaz, J Zambreno, G Memik, A Choudhary
2006 IEEE International Symposium on Workload Characterization, 182-188, 2006
Exploring area/delay tradeoffs in an AES FPGA implementation
J Zambreno, D Nguyen, A Choudhary
International Conference on Field Programmable Logic and Applications, 575-585, 2004
An FPGA-based network intrusion detection architecture
A Das, D Nguyen, J Zambreno, G Memik, A Choudhary
IEEE Transactions on Information Forensics and Security 3 (1), 118-132, 2008
A case study in hardware Trojan design and implementation
A Baumgarten, M Steffen, M Clausman, J Zambreno
International Journal of Information Security 10 (1), 1-14, 2011
An FPGA implementation of decision tree classification
R Narayanan, D Honbo, G Memik, A Choudhary, J Zambreno
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
A chaotic encryption scheme for real-time embedded systems: design and implementation
A Pande, J Zambreno
Telecommunication Systems 52 (2), 551-561, 2013
SAFE-OPS: An approach to embedded software security
J Zambreno, A Choudhary, R Simha, B Narahari, N Memon
ACM Transactions on Embedded Computing Systems (TECS) 4 (1), 189-210, 2005
Cygraph: A reconfigurable architecture for parallel breadth-first search
OG Attia, T Johnson, K Townsend, P Jones, J Zambreno
2014 IEEE International Parallel & Distributed Processing Symposium …, 2014
Securing multimedia content using joint compression and encryption
A Pande, P Mohapatra, J Zambreno
IEEE MultiMedia 20 (4), 50-61, 2012
Providing secure execution environments with a last line of defense against trojan circuit attacks
G Bloom, B Narahari, R Simha, J Zambreno
computers & security 28 (7), 660-669, 2009
Detecting/preventing information leakage on the memory bus due to malicious hardware
A Das, G Memik, J Zambreno, A Choudhary
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Design and analysis of a reconfigurable platform for frequent pattern mining
S Sun, J Zambreno
IEEE Transactions on Parallel and Distributed Systems 22 (9), 1497-1505, 2011
A floating-point accumulator for FPGA-based high performance computing applications
S Sun, J Zambreno
Proceedings of the International Conference on Field-Programmable Technology …, 2009
CODESSEAL: Compiler/FPGA approach to secure applications
O Gelbart, P Ott, B Narahari, R Simha, A Choudhary, J Zambreno
International Conference on Intelligence and Security Informatics, 530-535, 2005
An architectural characterization study of data mining and bioinformatics workloads
B Ozisikyilmaz, R Narayanan, J Zambreno, G Memik, A Choudhary
2006 IEEE International Symposium on Workload Characterization, 61-70, 2006
Improving simt efficiency of global rendering algorithms with architectural support for dynamic micro-kernels
M Steffen, J Zambreno
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 237-248, 2010
Dynamic simulation of electric machines on FPGA boards
H Chen, S Sun, DC Aliprantis, J Zambreno
2009 IEEE International Electric Machines and Drives Conference, 1523-1528, 2009
The secure wavelet transform
A Pande, J Zambreno
Embedded Multimedia Security Systems, 67-89, 2013
An efficient FPGA implementation of principle component analysis based network intrusion detection system
A Das, S Misra, S Joshi, J Zambreno, G Memik, A Choudhary
Proceedings of the conference on Design, automation and test in Europe, 1160 …, 2008
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