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Mário Véstias
Mário Véstias
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Title
Cited by
Cited by
Year
Trends of CPU, GPU and FPGA for high-performance computing
M Vestias, H Neto
2014 24th International Conference on Field Programmable Logic and …, 2014
1292014
A survey of convolutional neural networks on edge with reconfigurable computing
MP Véstias
Algorithms 12 (8), 154, 2019
1142019
Moving deep learning to the edge
MP Véstias, RP Duarte, JT de Sousa, HC Neto
Algorithms 13 (5), 125, 2020
622020
A full featured configurable accelerator for object detection with YOLO
D Pestana, PR Miranda, JD Lopes, RP Duarte, MP Véstias, HC Neto, ...
IEEE Access 9, 75864-75877, 2021
442021
Decimal multiplier on FPGA using embedded binary multipliers
HC Neto, MP Véstias
2008 International Conference on Field Programmable Logic and Applications …, 2008
442008
Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers
MP Véstias, HC Neto
Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational …, 2010
43*2010
Parallel decimal multipliers using binary multipliers
MP Véstias, HC Neto
2010 VI Southern Programmable Logic Conference (SPL), 73-78, 2010
412010
Predicting calcium in grape must and base wine by FT-NIR spectroscopy
J Véstia, JM Barroso, H Ferreira, L Gaspar, AE Rato
Food chemistry 276, 71-76, 2019
392019
Multi-core for K-means clustering on FPGA
J Canilho, M Véstias, H Neto
2016 26th International Conference on Field Programmable Logic and …, 2016
352016
Architectures and compilers to support reconfigurable computing
JMP Cardoso, MP Vestístias
XRDS: Crossroads, The ACM Magazine for Students 5 (3), 15-22, 1999
341999
Parallel dot-products for deep learning on FPGA
M Véstias, RP Duarte, JT de Sousa, H Neto
2017 27th international conference on field programmable logic and …, 2017
332017
Double-precision gauss-jordan algorithm with partial pivoting on fpgas
R Duarte, H Neto, M Véstias
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
282009
Area and performance optimization of a generic network-on-chip architecture
MP Véstias, HC Neto
Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006
272006
A review of synthetic-aperture radar image formation algorithms and implementations: A computational perspective
H Cruz, M Véstias, J Monteiro, H Neto, RP Duarte
Remote Sensing 14 (5), 1258, 2022
242022
A fast and scalable architecture to run convolutional neural networks in low density FPGAs
MP Véstias, RP Duarte, JT de Sousa, HC Neto
Microprocessors and Microsystems 77, 103136, 2020
222020
Lite-CNN: A high-performance architecture to execute CNNs in low density FPGAs
M Véstias, RP Duarte, JT de Sousa, H Neto
2018 28th International Conference on Field Programmable Logic and …, 2018
222018
Iterative decimal multiplication using binary arithmetic
MP Véstias, HC Neto
2011 VII Southern Conference on Programmable Logic (SPL), 257-262, 2011
212011
Co-synthesis of a configurable SoC platform based on a network on chip architecture
MP Véstias, HC Neto
Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006
212006
Revisiting the Newton-Raphson iterative method for decimal division
MP Vestias, HC Neto
2011 21st International Conference on Field Programmable Logic and …, 2011
202011
Fast convolutional neural networks in low density FPGAs using zero-skipping and weight pruning
MP Véstias, RP Duarte, JT de Sousa, HC Neto
Electronics 8 (11), 1321, 2019
162019
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