Carl Ramey
Carl Ramey
VP of Engineering, Lightmatter Inc.
Verified email at lightmatter.ai
Title
Cited by
Cited by
Year
On-chip interconnection architecture of the tile processor
D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ...
IEEE micro 27 (5), 15-31, 2007
10792007
Tile64-processor: A 64-core soc with mesh interconnect
S Bell, B Edwards, J Amann, R Conlin, K Joyce, V Leung, J MacKay, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
8012008
Computing in parallel processing environments
PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ...
US Patent 8,738,860, 2014
2302014
Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 microprocessor
S Taylor, M Quinn, D Brown, N Dohm, S Hildebrandt, J Huggins, C Ramey
Proceedings of the 35th annual Design Automation Conference, 638-643, 1998
1211998
Tile processor: Embedded multicore for networking and multimedia
A Agarwal, L Bao, J Brown, B Edwards, M Mattina, CC Miao, C Ramey, ...
Hot Chips 19, 2007
852007
Coupling integrated circuits in a parallel processing environment
D Wentzlaff, CG Ramey, A Agarwal
US Patent 7,539,845, 2009
812009
Tile-gx100 manycore processor: Acceleration interfaces and architecture
C Ramey
2011 IEEE Hot Chips 23 Symposium (HCS), 1-21, 2011
772011
High performance, scalable multi chip interconnect
CG Ramey, M Mattina
US Patent 9,424,228, 2016
642016
Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip
C Ramey
US Patent 7,552,241, 2009
442009
Condensed router headers with low latency output port calculation
IR Bratt, CG Ramey, M Mattina
US Patent 8,572,353, 2013
302013
Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors
MC Mattina, C Ramey, B Jung, J Leonard
US Patent 7,620,954, 2009
242009
Managing cache access and streaming data
CC Miao, CD Metcalf, IR Bratt, CG Ramey
US Patent App. 10/210,092, 2019
23*2019
Coupling data in a parallel processing environment
CG Ramey, D Wentzlaff, A Agarwal
US Patent 7,636,835, 2009
232009
Computing in parallel processing environments
CG Ramey, CD Metcalf
US Patent App. 10/037,299, 2018
17*2018
Managing cache coherence
CC Miao, CD Metcalf, IR Bratt, CG Ramey
US Patent 8,521,963, 2013
152013
A simulation-based method for the verification of shared memory in multiprocessor systems
S Taylor, C Ramey, C Barner, D Asher
IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE …, 2001
142001
Computing in parallel processing environments
CG Ramey
US Patent App. 10/078,613, 2018
12*2018
Managing cache access and streaming data
CC Miao, CD Metcalf, IR Bratt, CG Ramey
US Patent 9,213,652, 2015
112015
Configurable device interfaces
PR Griffin, CG Ramey
US Patent 8,799,624, 2014
112014
Managing home cache assignment
CC Miao, CD Metcalf, IR Bratt, CG Ramey
US Patent 8,539,155, 2013
112013
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