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Kohei Matsuda
Kohei Matsuda
Verified email at cs26.scitec.kobe-u.ac.jp
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Cited by
Cited by
Year
A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor
K Matsuda, T Fujii, N Shoji, T Sugawara, K Sakiyama, YI Hayashi, ...
IEEE Journal of Solid-State Circuits 53 (11), 3174-3182, 2018
352018
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression
R Ueno, S Morioka, N Miura, K Matsuda, M Nagata, S Bhasin, Y Mathieu, ...
IEEE Transactions on Computers 69 (4), 534-548, 2019
312019
A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar
N Miura, T Machida, K Matsuda, M Nagata, S Nashimoto, D Suzuki
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware …, 2019
292019
Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure
S Nashimoto, D Suzuki, N Miura, T Machida, K Matsuda, M Nagata
Journal of Cryptographic Engineering 11 (3), 289-298, 2021
232021
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor
N Miura, D Fujimoto, R Korenaga, K Matsuda, M Nagata
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 225-228, 2014
202014
On-chip substrate-bounce monitoring for laser-fault countermeasure
K Matsuda, N Miura, M Nagata, Y Hayashi, T Fujii, K Sakiyama
2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 1-6, 2016
192016
An IC-level countermeasure against laser fault injection attack by information leakage sensing based on laser-induced opto-electric bulk current density
K Matsuda, S Tada, M Nagata, Y Komano, Y Li, T Sugawara, M Iwamoto, ...
Japanese Journal of Applied Physics 59 (SG), SGGL02, 2020
152020
Side-channel leakage from sensor-based countermeasures against fault injection attack
T Sugawara, N Shoji, K Sakiyama, K Matsuda, N Miura, M Nagata
Microelectronics Journal 90, 63-71, 2019
122019
A 286F2/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack
K Matsuda, T Fujii, N Shoji, T Sugawara, K Sakiyama, Y Hayashi, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 352-354, 2018
112018
A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor
N Miura, K Matsuda, M Nagata, S Bhasin, V Yli-Mayry, N Homma, ...
2017 Symposium on VLSI Circuits, C266-C267, 2017
112017
Design and concept proof of an inductive impulse self-destructor in sense-and-react countermeasure against physical attacks
S Tada, Y Yamashita, K Matsuda, M Nagata, K Sakiyama, N Miura
Japanese Journal of Applied Physics 60 (SB), SBBL01, 2021
82021
Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis
T Sugawara, N Shoji, K Sakiyama, K Matsuda, N Miura, M Nagata
2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 49-56, 2017
82017
An information leakage sensor based on measurement of laser-induced opto-electric bulk current density
K Matsuda, S Tada, M Nagata, Y Li, T Sugawara, M Iwamoto, K Ohta, ...
Int. Conf. on Solid State Devices and Materials (SSDM) Extended Abstracts …, 2019
5*2019
Side-channel leakage of alarm signal for a bulk-current-based laser sensor
Y Li, R Hatano, S Tada, K Matsuda, N Miura, T Sugawara, K Sakiyama
International Conference on Information Security and Cryptology, 346-361, 2020
42020
An Inductive Impulse Self-Destructor in Sense-and-React Countermeasure Against Physical Attacks
SHO TADA, K MATSUDA, M NAGATA, K SAKIYAMA, N MIURA
電子情報通信学会技術研究報告 119 (443 (VLD2019 94-144)), 275-277, 2020
22020
Flush Code Eraser: Fast Attack Response Invalidating Cryptographic Sensitive Data
K Sakiyama, T Fujii, K Matsuda, N Miura
IEEE Embedded Systems Letters 12 (2), 37-40, 2019
12019
Light-Weight Design Methodology of Bulk Current Sensor Against Laser Fault Injection Attack on Cryptographic Processor
Y Yamashita, K Matsuda, M Nagata, N Miura
IEICE Technical Report; IEICE Tech. Rep. 119 (444), 283-284, 2020
2020
Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset
R Ueno, S Morioka, N Miura, K Matsuda, M Nagata, S Bhasin, Y Mathieu, ...
IEICE Technical Report; IEICE Tech. Rep. 119 (143), 375-382, 2019
2019
An ultra-light weight implementation of PRINCE-family cryptographic processor
K Matsuda, M Nagata, N Miura
IEICE Technical Report; IEICE Tech. Rep. 118 (458), 261-265, 2019
2019
レーザー故障注入攻撃対策を備えた暗号 IC の設計手法
松田航平, 藤井達哉, 庄司奈津, 菅原健, 崎山一男, 林優一, 永田真, ...
DA シンポジウム 2018 論文集 2018, 220-225, 2018
2018
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