| Very low power pipelines using significance compression R Canal, A González, JE Smith Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000 | 170 | 2000 |
| Dynamic cluster assignment mechanisms R Canal, JM Parcerisa, A González Proceedings Sixth International Symposium on High-Performance Computer …, 2000 | 166 | 2000 |
| Process variation tolerant 3T1D-based cache architectures X Liang, R Canal, GY Wei, D Brooks 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007 | 135 | 2007 |
| A low-complexity issue logic R Canal, A González Proceedings of the 14th international conference on Supercomputing, 327-335, 2000 | 133 | 2000 |
| Design space exploration for multicore architectures: a power/performance/thermal view M Monchiero, R Canal, A González Proceedings of the 20th annual international conference on Supercomputing …, 2006 | 125 | 2006 |
| Power/performance/thermal design-space exploration for multicore architectures M Monchiero, R Canal, A Gonzalez IEEE Transactions on Parallel and Distributed Systems 19 (5), 666-681, 2008 | 88 | 2008 |
| Reducing the complexity of the issue logic R Canal, A González Proceedings of the 15th International conference on Supercomputing, 312-320, 2001 | 87 | 2001 |
| A cost-effective clustered architecture R Canal, JM Parcerisa, A Gonzalez 1999 International Conference on Parallel Architectures and Compilation …, 1999 | 87 | 1999 |
| An energy-efficient and scalable eDRAM-based register file architecture for GPGPU N Jing, Y Shen, Y Lu, S Ganapathy, Z Mao, M Guo, R Canal, X Liang ACM SIGARCH Computer Architecture News 41 (3), 344-355, 2013 | 85 | 2013 |
| Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors E Herrero, J González, R Canal Proceedings of the 37th annual international symposium on Computer …, 2010 | 84 | 2010 |
| Distributed cooperative caching E Herrero, J González, R Canal Proceedings of the 17th international conference on Parallel architectures …, 2008 | 70 | 2008 |
| Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability X Liang, R Canal, GY Wei, D Brooks IEEE micro 28 (1), 60-68, 2008 | 53 | 2008 |
| Merlin: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment M Kaliorakis, D Gizopoulos, R Canal, A Gonzalez Proceedings of the 44th Annual International Symposium on Computer …, 2017 | 49 | 2017 |
| Power-and complexity-aware issue queue designs J Abella Ferrer, R Canal Corretger, AM González Colás IEEE micro 23 (5), 50-58, 2003 | 47 | 2003 |
| An hybrid eDRAM/SRAM macrocell to implement first-level data caches A Valero, J Sahuquillo, S Petit, V Lorente, R Canal, P López, J Duato Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 46 | 2009 |
| Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability S Ganapathy, R Canal, A Gonzalez, A Rubio 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 37 | 2010 |
| A detailed methodology to compute soft error rates in advanced technologies M Riera, R Canal, J Abella, A Gonzalez 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 217-222, 2016 | 32 | 2016 |
| Dynamic code partitioning for clustered architectures R Canal, JM Parcerisa, A González International Journal of Parallel Programming 29 (1), 59-79, 2001 | 31 | 2001 |
| SyRA: Early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems A Vallero, A Savino, A Chatzidimitriou, M Kaliorakis, M Kooli, M Riera, ... IEEE Transactions on Computers 68 (5), 765-783, 2018 | 29 | 2018 |
| Cross-layer system reliability assessment framework for hardware faults A Vallero, A Savino, G Politano, S Di Carlo, A Chatzidimitriou, S Tselonis, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 29 | 2016 |
