| Controlling aging in timing-critical paths S Arasu, M Nourani, JM Carulli, VK Reddy IEEE Design & Test 33 (4), 82-91, 2015 | 20 | 2015 |
| Method and apparatus to use physical design information to detect IR drop prone test patterns SA Thirunavukarasu, S Bhabu, V Chickermane US Patent 7,877,715, 2011 | 15 | 2011 |
| Efficient calculation of a number of transitions and estimation of power dissipation in sequential scan tests SA Thirunavukarasu, D Varadarajan US Patent 7,277,803, 2007 | 13 | 2007 |
| A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer ST Arasu, CP Ravikumar, SK Nandy IEEE International Conference on Test, 2005., 9 pp.-377, 2005 | 11 | 2005 |
| A design-for-reliability approach based on grading library cells for aging effects S Arasu, M Nourani, JM Carulli, KM Butler, V Reddy 2013 IEEE International Test Conference (ITC), 1-7, 2013 | 9 | 2013 |
| Performance entitlement by exploiting transistor's BTI recovery S Arasu, M Nourani, V Reddy, JM Carulli International Symposium on Quality Electronic Design (ISQED), 341-346, 2013 | 9 | 2013 |
| Asymmetric aging of clock networks in power efficient designs S Arasu, M Nourani, F Cano, JM Carulli, V Reddy Fifteenth International Symposium on Quality Electronic Design, 484-489, 2014 | 8 | 2014 |
| Testing to prescribe state capture by, and state retrieval from scan registers SA Thirunavukarasu, V Chickermane, S Bhabu US Patent 7,886,263, 2011 | 8 | 2011 |
| Method and apparatus to detect manufacturing faults in power switches SA Thirunavukarasu, BCC Leung, S Bhabu, V Chickermane US Patent 7,944,285, 2011 | 5 | 2011 |
| Sequential scan technique for testing integrated circuits with reduced power, time and/or cost D Varadarajan, SA Thirunavukarasu US Patent 7,555,687, 2009 | 4 | 2009 |
| Reliability improvement of logic and clock paths in power-efficient designs S Arasu, M Nourani, V Reddy, JMC Jr, G Kapila, M Chen ACM Journal on Emerging Technologies in Computing Systems (JETC) 10 (1), 1-23, 2014 | 3 | 2014 |
| Automating optimal placement of macro-blocks in the design of an integrated circuit T Meyyappan, SA Thirunavukarasu, SM Katla, RS Guzar US Patent 7,596,773, 2009 | 3 | 2009 |
| An all-digital adaptive approach to combat aging effects in clock networks S Arasu, M Nourani, H Luo 2015 6th Asia symposium on quality electronic design (ASQED), 102-107, 2015 | 2 | 2015 |
| Method and apparatus to use physical design information to detect IR drop prone test patterns SA Thirunavukarasu, S Bhabu, V Chickermane US Patent 8,392,868, 2013 | 2 | 2013 |
| Scan test power estimation and optimization CP Ravikumar, S Arasu, T Srinivas Proceedings of the Synopsys User Group Conference, 2003 | 2 | 2003 |
| Low-power hierarchical scan test for multiple clock domains TS Arasu, CP Ravikumar, SK Nandy Journal of Low Power Electronics 3 (1), 106-118, 2007 | 1 | 2007 |
