| A tool for calculating energy consumption in wireless sensor networks G Dimitriou, PK Kikiras, GI Stamoulis, IN Avaritsiotis Panhellenic Conference on Informatics, 611-621, 2005 | 14 | 2005 |
| AGP: a parallel processor for knowledge and software engineering G Papakonstantinou, T Panayiotopoulos, G Dimitriou The Computer Journal 35 (2), 1992 | 8 | 1992 |
| Experimenting with a high-level synthesis system front end G Dimitriou, M Dossis PACET 2015, 2015 | 6 | 2015 |
| Loop scheduling for multithreaded processors G Dimitriou, C Polychronopoulos Parallel Computing in Electrical Engineering, 2004. International Conference …, 2004 | 4 | 2004 |
| Placement-based SER estimation in the presence of multiple faults in combinational logic GI Paliaroutis, P Tsoumanis, N Evmorfopoulos, G Dimitriou, GI Stamoulis 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 3 | 2017 |
| Minimal-area loop pipelining for high-level synthesis with CCC G Dimitriou, M Dossis, G Stamoulis 2017 South Eastern European Design Automation, Computer Engineering …, 2017 | 3 | 2017 |
| Performance and power simulation of a functional-unit-network processor with simplescalar and wattch K Kalaitzidis, G Dimitriou, G Stamoulis, M Dossis Proceedings of the 19th Panhellenic Conference on Informatics, 71-76, 2015 | 3 | 2015 |
| A placement-aware soft error rate estimation of combinational circuits for multiple transient faults in CMOS technology GI Paliaroutis, P Tsoumanis, N Evmorfopoulos, G Dimitriou, GI Stamoulis 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2018 | 2 | 2018 |
| Loop pipelining in high-level synthesis with CCC G Dimitriou, M Dossis, G Stamoulis 2017 6th International Conference on Modern Circuits and Systems …, 2017 | 2 | 2017 |
| Loop scheduling for multithreaded processors. G Dimitriou | 2 | 2001 |
| Simulation of static and dynamic task scheduling of multiprocessor systems G Dimitriou University of Illinois at Urbana-Champaign, 1994 | 2 | 1994 |
| Multiple Transient Faults in Combinational Logic with Placement Considerations GI Paliaroutis, P Tsoumanis, N Evmorfopoulos, G Dimitriou, GI Stamoulis 2019 8th International Conference on Modern Circuits and Systems …, 2019 | 1 | 2019 |
| SER Analysis of Multiple Transient Faults in Combinational Logic GI Paliaroutis, P Tsoumanis, G Dimitriou, GI Stamoulis Proceedings of the SouthEast European Design Automation, Computer …, 2016 | 1 | 2016 |
| Source-level compiler optimizations for high-level synthesis G Dimitriou, G Chatzianastasiou, A Tsakyridis, G Stamoulis, M Dossis Proceedings of the SouthEast European Design Automation, Computer …, 2016 | 1 | 2016 |
| Hardware synthesis of high-level C constructs M Dossis, G Dimitriou Proceedings of the 19th Panhellenic Conference on Informatics, 83-85, 2015 | 1 | 2015 |
| Electromigration: Estimation methodology for the sub-45nm era G Floros, G Dimitriou, GI Stamoulis The International Conference on Computer Science, Computer Engineering, and …, 2014 | 1 | 2014 |
| Rapid, low-power loop execution in a network of functional units A Tziouvaras, G Dimitriou Proceedings of the 17th Panhellenic Conference on Informatics, 211-218, 2013 | 1 | 2013 |
| SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations GI Paliaroutis, P Tsoumanis, N Evmorfopoulos, G Dimitriou, GI Stamoulis Technologies 8 (1), 5, 2020 | | 2020 |
| Instruction-Flow-Based Timing Analysis in Pipelined Processors A Tziouvaras, G Dimitriou, M Dossis, G Stamoulis 2019 Panhellenic Conference on Electronics & Telecommunications (PACET), 1-6, 2019 | | 2019 |
| Operation Dependencies in Loop Pipelining for High-Level Synthesis G Dimitriou, M Dossis, G Stamoulis 2018 South-Eastern European Design Automation, Computer Engineering …, 2018 | | 2018 |
