| Glitch-aware pattern generation and optimization framework for power-safe scan test VR Devanathan, CP Ravikumar, V Kamakoti 25th IEEE VLSI Test Symposium (VTS'07), 167-172, 2007 | 52 | 2007 |
| A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test VR Devanathan, CP Ravikumar, V Kamakoti 2007 IEEE International Test Conference, 1-10, 2007 | 33 | 2007 |
| On power-profiling and pattern generation for power-safe scan tests VR Devanathan, CP Ravikumar, V Kamakoti 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 33 | 2007 |
| PMScan: A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test VR Devanathan, CP Ravikumar, R Mehrotra, V Kamakoti 2007 IEEE International Test Conference, 1-9, 2007 | 30 | 2007 |
| Methodology for low power test pattern generation using activity threshold control logic S Ravi, VR Devanathan, R Parekhji 2007 IEEE/ACM International Conference on Computer-Aided Design, 526-529, 2007 | 24 | 2007 |
| Reducing SoC test time and test power in hierarchical scan test: Scan architecture and algorithms VR Devanathan, CP Ravikumar, V Kamakoti 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 22 | 2007 |
| DFT techniques to reduce test time and power for SoCs D Varadarajan, CP Ravikumar US Patent 7,949,920, 2011 | 13* | 2011 |
| Efficient calculation of a number of transitions and estimation of power dissipation in sequential scan tests S Arasu Thirunavukarasu, D Varadarajan US Patent 7,277,803, 2007 | 13 | 2007 |
| OPTIMIZING fuseROM USAGE FOR MEMORY REPAIR D Varadarajan, H ELLUR US Patent 9,053,799, 2015 | 12 | 2015 |
| Variation-tolerant, power-safe pattern generation VR Devanathan, CP Ravikumar, V Kamakoti IEEE design & test 24 (4), 374-384, 2007 | 12 | 2007 |
| Centralized built-in soft-repair architecture for integrated circuits with embedded memories D Varadarajan, SD Kale US Patent 10,134,483, 2018 | 11 | 2018 |
| Sequential Scan Technique Providing Reliable Testing of an Integrated Circuit D Varadarajan, CP Ravikumar US Patent App. 11/567,751, 2008 | 11 | 2008 |
| Hierarchical, Distributed Built-in Self-Repair Solution D Varadarajan, R Prasad KS, H Ellur US Patent 9,318,222, 2016 | 10 | 2016 |
| Towards effective and compression-friendly test of memory interface logic VR Devanathan, A Hales, S Kale, D Sonkar 2010 IEEE International Test Conference, 1-10, 2010 | 9 | 2010 |
| Scan-enabled method and system for testing a system-on-chip D Varadarajan, B Dibbur NARASINGARAO, V Narendra PATIL US Patent 8,051,347, 2011 | 8 | 2011 |
| Prowatch: a proactive cross-layer workload-aware temperature management framework for low-power chip multi-processors M Patnaik, C Garg, A Roy, VR Devanathan, S Balachandran, V Kamakoti ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (3), 1-25, 2015 | 7 | 2015 |
| New methods for simulation speed-up and test qualification with analog fault simulation VR Devanathan, L Balasubramanian, R Parekhji 2015 28th International Conference on VLSI Design, 363-368, 2015 | 7 | 2015 |
| Optimizing fuseROM usage for memory repair D Varadarajan, H Ellur US Patent 9,852,810, 2017 | 6 | 2017 |
| A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath VR Devanathan, S Kale 2016 IEEE International Test Conference (ITC), 1-6, 2016 | 6 | 2016 |
| SER mitigation technique through selective flip-flop replacement PV Torvi, VR Devanathan, A Vanjari, V Kamakoti 2015 6th Asia Symposium on Quality Electronic Design (ASQED), 25-30, 2015 | 6 | 2015 |
