Reconfigurable processing AR Dasu, A Akoglu, A Sudarsanam, S Panchanathan US Patent 8,281,297, 2012 | 234 | 2012 |
Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms A Sudarsanam, R Barnes, J Carver, R Kallam, A Dasu IET computers & digital techniques 4 (2), 126-142, 2010 | 43 | 2010 |
PRR-PRR dynamic relocation A Sudarsanam, R Kallam, A Dasu IEEE Computer Architecture Letters 8 (2), 44-47, 2009 | 28 | 2009 |
Resource estimation and task scheduling for multithreaded reconfigurable architectures A Sudarsanam, M Srinivasan, S Panchanathan Proceedings. Tenth International Conference on Parallel and Distributed …, 2004 | 27 | 2004 |
Performance of a LU decomposition on a multi-FPGA system compared to a low power commodity microprocessor system T Hauser, A Dasu, A Sudarsanam, S Young Scalable Computing: Practice and Experience 8 (4), 2007 | 15 | 2007 |
High level-application analysis techniques & architectures-to explore design possibilities for reduced reconfiguration area overheads in FPGAs executing compute intensive … D Aravind, A Sudarsanam 19th IEEE International Parallel and Distributed Processing Symposium, 8 pp., 2005 | 13 | 2005 |
Analysis of field programmable gate array-based kalman filter architectures A Sudarsanam Utah State University, 2010 | 9 | 2010 |
Methodology to derive context adaptable architectures for FPGAs J Phillips, A Sudarsanam, H Samala, R Kallam, J Carver, A Dasu IET Computers & Digital Techniques 3 (1), 124-141, 2009 | 7 | 2009 |
A Power Efficient Linear Equation Solver on A Multi-Fpgaaccelerator A Sudarsanam, T Hauser, A Dasu, S Young International Journal of Computers and Applications 32 (1), 56-72, 2010 | 5 | 2010 |
Memory architecture template for Fast Block Matching algorithms on FPGAs S Chandrakar, A Clements, A Sudarsanam, A Dasu 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010 | 3 | 2010 |
A fast and efficient fpga-based implementation for solving a system of linear interval equations A Sudarsanam, D Aravind Proceedings. 2005 IEEE International Conference on Field-Programmable …, 2005 | 3 | 2005 |
Pattern recognition tool to detect reconfigurable patterns in MPEG4 video processing A Akoglu, A Dasu, A Sudarsanam, M Srinivasan, S Panchanathan Parallel and Distributed Processing Symposium, International 3, 0131-0131, 2002 | 3 | 2002 |
Memory support design for LU decomposition on the starbridge hyper-computer S Young, A Sudarsanam, A Dasu, T Hauser 2006 IEEE International Conference on Field Programmable Technology, 157-164, 2006 | 2 | 2006 |
Multi-FPGA based High Performance LU Decomposition A Sudarsanam, S Young, A Dasu, T Hauser 10th High Performance Embedded Computing (HPEC) workshop, 2006 | 2 | 2006 |
Design of embedded compute-intensive processing elements and their scheduling in a reconfigurable environment A Dasu, A Sudarsanam, S Panchanathan Canadian Journal of Electrical and Computer Engineering 30 (2), 103-113, 2005 | 2 | 2005 |
Analysis and design of a context adaptable SAD/MSE architecture A Sudarsanam, A Dasu, K Vaithianathan International Journal of Reconfigurable Computing 2009, 2009 | 1 | 2009 |
Task scheduling of control-data flow graphs for reconfigurable architectures A Sudarsanam, D Aravind, S Panchanathan Proceedings of the International Conference on Engineering of Reconfigurable …, 2004 | 1 | 2004 |
Reconfigurable Processing A Dasu, A Akoglu, A Sudarsanam, S Panchanathan | 1 | 1800 |
Near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine K Vaithianathan, A Sudarsanam US Patent 9,658,829, 2017 | | 2017 |
A novel predicated data flow analysis based memory design for data-and control-intensive multimedia applications A Sudarsanam, S Panchanathan Embedded Processors for Multimedia and Communications II 5683, 64-71, 2005 | | 2005 |