| Neural networks at work D Hammerstrom IEEE spectrum 30 (6), 26-32, 1993 | 401 | 1993 |
| A VLSI architecture for high-performance, low-cost, on-chip learning D Hammerstrom 1990 IJCNN International Joint Conference on Neural Networks, 537-544, 1990 | 382 | 1990 |
| Working with neural networks D Hammerstrom IEEE spectrum 30 (7), 46-53, 1993 | 363 | 1993 |
| Coupled-oscillator associative memory array operation for pattern recognition DE Nikonov, G Csaba, W Porod, T Shibata, D Voils, D Hammerstrom, ... IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 1 …, 2015 | 193 | 2015 |
| Architectures for silicon nanoelectronics and beyond RI Bahar, D Hammerstrom, J Harlow, WH Joyner, C Lau, D Marculescu, ... Computer 40 (1), 25-33, 2007 | 113 | 2007 |
| Information content of CPU memory referencing behavior DW Hammerstrom, ES Davidson Proceedings of the 4th annual symposium on Computer architecture, 184-192, 1977 | 94 | 1977 |
| Why VLSI implementations of associative VLCNs require connection multiplexing Hammerstrom IEEE 1988 International Conference on Neural Networks, 173-180 vol. 2, 1988 | 85 | 1988 |
| A highly parallel digital architecture for neural network emulation D Hammerstrom VLSI for Artificial Intelligence and Neural Networks, 357-366, 1991 | 79 | 1991 |
| An 11-million transistor neural network execution engine M Griffin, G Tahara, K Knorpp, R Pinkham, B Riley 1991 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1991 | 76 | 1991 |
| Image processing using one-dimensional processor arrays DW Hammerstrom, DP Lulich Proceedings of the IEEE 84 (7), 1005-1018, 1996 | 63 | 1996 |
| Cortical models onto CMOL and CMOS—architectures and performance/price C Gao, D Hammerstrom IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2502-2515, 2007 | 61 | 2007 |
| Defect-tolerant CMOL cell assignment via satisfiability WNN Hung, C Gao, X Song, D Hammerstrom IEEE Sensors Journal 8 (6), 823-830, 2008 | 57 | 2008 |
| An implementation of Kohonen's self-organizing map on the Adaptive Solutions neurocomputer D Hammerstrom, N Nguyen Kohonen et al, 715-720, 1991 | 56 | 1991 |
| The connectivity analysis of simple association D Hammerstrom Neural Information Processing Systems, 1987 | 54 | 1987 |
| Hebbian feature discovery improves classifier efficiency T Leen, M Rudnick, D Hammerstrom 1990 IJCNN International Joint Conference on Neural Networks, 51-56, 1990 | 52 | 1990 |
| Supporting Ada memory management in the iAPX-432 FJ Pollack, GW Cox, DW Hammerstrom, KC Kahn, KK Lai, JR Rattner ACM SIGARCH Computer Architecture News 10 (2), 117-131, 1982 | 46 | 1982 |
| Digital VLSI for neural networks D Hammerstrom The handbook of brain theory and neural networks, 304-309, 2003 | 42 | 2003 |
| A digital VLSI architecture for real-world applications D Hammerstrom An introduction to neural and electronic networks, 335-358, 1995 | 34 | 1995 |
| Distributing back propagation networks over the Intel iPSC/860 hypercube D Jackson, D Hammerstrom IJCNN-91-Seattle International Joint Conference on Neural Networks 1, 569-574, 1991 | 34 | 1991 |
| Methodology and design of a massively parallel memristive stateful IMPLY logic-based reconfigurable architecture KC Rahman, D Hammerstrom, Y Li, H Castagnaro, MA Perkowski IEEE Transactions on Nanotechnology 15 (4), 675-686, 2016 | 33 | 2016 |
