Optimal selective Huffman coding for test-data compression X Kavousianos, E Kalligeros, D Nikolos IEEE transactions on computers 56 (8), 1146-1152, 2007 | 163 | 2007 |
Multilevel Huffman coding: An efficient test-data compression method for IP cores X Kavousianos, E Kalligeros, D Nikolos IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 66 | 2007 |
Test data compression based on variable-to-variable Huffman encoding with codeword reusability X Kavousianos, E Kalligeros, D Nikolos IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 52 | 2008 |
Multilevel-Huffman test-data compression for IP cores with multiple scan chains X Kavousianos, E Kalligeros, D Nikolos IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (7), 926-931, 2008 | 48 | 2008 |
Test schedule optimization for multicore SoCs: Handling dynamic voltage scaling and multiple voltage islands X Kavousianos, K Chakrabarty, A Jain, R Parekhji IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 33 | 2012 |
Multiphase BIST: A new reseeding technique for high test-data compression E Kalligeros, X Kavousianos, D Nikolos IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 33 | 2004 |
State skip LFSRs: Bridging the gap between test data compression and test set embedding for IP cores V Tenentes, X Kavousianos, E Kalligeros Proceedings of the conference on Design, automation and test in Europe, 474-479, 2008 | 30 | 2008 |
An efficient seeds selection method for LFSR-based test-per-clock BIST E Kalligeros, X Kavousianos, D Bakalis, D Nikolos Proceedings International Symposium on Quality Electronic Design, 261-266, 2002 | 30 | 2002 |
Efficient partial scan cell gating for low-power scan-based testing X Kavousianos, D Bakalis, D Nikolos ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (2 …, 2009 | 29 | 2009 |
Single and variable-state-skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores V Tenentes, X Kavousianos, E Kalligeros IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 28 | 2010 |
Reseeding-based test set embedding with reduced test sequences E Kalligeros, D Kaseridis, X Kavousianos, D Nikolos Sixth international symposium on quality electronic design (isqed'05), 226-231, 2005 | 26 | 2005 |
On the design of self-testing checkers for modified Berger codes SJ Piestrak, D Bakalis, X Kavousianos Proceedings Seventh International On-Line Testing Workshop, 153-157, 2001 | 26 | 2001 |
On-the-fly reseeding: A new reseeding technique for test-per-clock BIST E Kalligeros, X Kavousianos, D Bakalis, D Nikolos Journal of Electronic Testing 18, 315-332, 2002 | 25 | 2002 |
The time dilation technique for timing error tolerance S Valadimas, A Floros, Y Tsiatouhas, A Arapoyanni, X Kavousianos IEEE Transactions on Computers 63 (5), 1277-1286, 2012 | 24 | 2012 |
Novel TSC Checkers for Bose-Lin and Bose Codes X Kavousianos, D Nikolos Proceedings of 3ed IEEE Int. On-Line Testing Workshop, 172-176, 1998 | 24 | 1998 |
Static power reduction using variation-tolerant and reconfigurable multi-mode power switches Z Zhang, X Kavousianos, K Chakrabarty, Y Tsiatouhas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (1), 13-26, 2013 | 23 | 2013 |
Defect aware x-filling for low-power scan testing S Balatsouka, V Tenentes, X Kavousianos, K Chakrabarty 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 23 | 2010 |
New reseeding technique for LFSR-based test pattern generation E Kalligeros, X Kavousianos, D Bakalis, D Nikolos Proceedings Seventh International On-Line Testing Workshop, 80-86, 2001 | 22 | 2001 |
Test scheduling for multicore SoCs with dynamic voltage scaling and multiple voltage islands X Kavousianos, K Chakrabarty, A Jain, R Parekhji 2011 Asian Test Symposium, 33-39, 2011 | 20 | 2011 |
A robust and reconfigurable multi-mode power gating architecture Z Zhang, X Kavousianos, K Chakrabarty, Y Tsiatouhas 2011 24th Internatioal Conference on VLSI Design, 280-285, 2011 | 20 | 2011 |