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A. SHEIBANYRAD
A. SHEIBANYRAD
CNRS Research Fellow / LIP6 Lab. / SoC Dept.
Verified email at lip6.fr
Title
Cited by
Cited by
Year
Elevator-first: A deadlock-free distributed routing algorithm for vertically partially connected 3d-nocs
F Dubois, A Sheibanyrad, F Petrot, M Bahmani
IEEE Transactions on Computers 62 (3), 609-615, 2011
1552011
A low cost network-on-chip with guaranteed service well suited to the GALS approach
IM Panades, A Greiner, A Sheibanyrad
2006 1st International Conference on Nano-Networks and Workshops, 1-5, 2006
1412006
3D integration for NoC-based SoC Architectures
A Sheibanyrad, F Pétrot, A Jantsch
Springer, 2011
1072011
Multisynchronous and fully asynchronous NoCs for GALS architectures
A Sheibanyrad, A Greiner, I Miro-Panades
IEEE Design & Test of Computers 25 (6), 572-580, 2008
852008
A 3D-NoC router implementation exploiting vertically-partially-connected topologies
M Bahmani, A Sheibanyrad, F Pétrot, F Dubois, P Durante
2012 IEEE Computer Society Annual Symposium on VLSI, 9-14, 2012
562012
A Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
P Vivet, Y Thonnart, R Lemaire, C Santos, E Beigné, C Bernard, F Darve, ...
IEEE Journal of Solid-State Circuits 52 (1), 33-49, 2016
552016
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
A Sheibanyrad, IM Panades, A Greiner
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
482007
Physical implementation of an asynchronous 3D-NoC router using serial vertical links
F Darve, A Sheibanyrad, P Vivet, F Pétrot
2011 IEEE Computer Society Annual Symposium on VLSI, 25-30, 2011
452011
Two efficient synchronous asynchronous converters well-suited for networks-on-chip in GALS architectures
A Sheibanyrad, A Greiner
Integration 41 (1), 17-26, 2008
392008
Assignment of vertical-links to routers in vertically-partially-connected 3-D-NoCs
S Foroutan, A Sheibanyrad, F Petrot
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
322014
Asynchronous implementation of a distributed network-on-chip
A Sheibanyrad
Pierre et Marie Curie (UPMC), 2008
16*2008
Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures.
A Sheibanyrad, A Greiner
ESA, 27-33, 2007
162007
Two efficient synchronous asynchronous converters well-suited for network on chip in GALS architectures
A Sheibanyrad, A Greiner
International Workshop on Power and Timing Modeling, Optimization and …, 2006
102006
Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces
S Foroutan, A Sheibanyrad, F Pétrot
Proceedings of the 49th Annual Design Automation Conference, 366-375, 2012
62012
Asynchronous 3D-NoCs making use of serialized vertical links
A Sheibanyrad, F Pétrot
3D Integration for NoC-based SoC Architectures, 149-165, 2011
62011
Abstract description of system application and hardware architecture for hardware/software code generation
A El Mrabti, H Sheibanyrad, F Rousseau, F Petrot, R Lemaire, J Martin
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
62009
Synthesis of dependency-aware traffic generators from NoC simulation traces
OA de Lima Jr, V Fresse, F Rousseau, H Sheibanyrad
Journal of Systems Architecture 71, 102-113, 2016
52016
Sérialiseur et desérialiseur asynchrone pour circuit intégré tridimensionnel
A Sheibanyrad, F Petrot
French Patent 9, 53637, 2009
42009
A meta-routing method to create multiple virtual logical networks on a single hardware noc
HB Amor, H Sheibanyrad, F Pétrot
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 200-205, 2017
12017
Micro-réseau sur puce compatible avec l˘approche GALS
IM Panades, A Greiner, S Abbas
JNRDM˘06: Journées Nationales du Réseau Doctoral en Microélectronique, 2006
12006
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