Matt Farrens
Matt Farrens
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα
Παρατίθεται από
Παρατίθεται από
A modified approach to data cache management
G Tyson, M Farrens, J Matthews, AR Pleszkun
Proceedings of the 28th annual international symposium on Microarchitecture …, 1995
HLS: Combining statistical and symbolic simulation to guide microprocessor designs
M Oskin, FT Chong, M Farrens
ACM SIGARCH Computer Architecture News 28 (2), 71-82, 2000
Eager writeback-a technique for improving bandwidth utilization
HHS Lee, GS Tyson, MK Farrens
Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000
Addressing system-level trimming issues in on-chip nanophotonic networks
C Nitta, M Farrens, V Akella
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
Dynamic base register caching: A technique for reducing address bus width
M Farrens, A Park
ACM SIGARCH Computer Architecture News 19 (3), 128-137, 1991
Utilizing reuse information in data cache management
JA Rivers, ES Tam, GS Tyson, ES Davidson, M Farrens
Proceedings of the 12th international conference on Supercomputing, 449-456, 1998
Strategies for achieving improved processor throughput
MK Farrens, AR Pleszkun
Proceedings of the 18th annual international symposium on Computer …, 1991
Simultaneously reducing latency and power consumption in openflow switches
PT Congdon, P Mohapatra, M Farrens, V Akella
IEEE/ACM Transactions On Networking 22 (3), 1007-1020, 2013
Branch transition rate: a new metric for improved branch classification analysis
M Haungs, P Sallee, M Farrens
Proceedings Sixth International Symposium on High-Performance Computer …, 2000
Limited dual path execution
G Tyson, K Lick, M Farrens
Technical Report CSE-TR 346-97, University of Michigan, 1997
MISC: A multiple instruction stream computer
G Tyson, M Farrens, AR Pleszkun
ACM SIGMICRO Newsletter 23 (1-2), 193-196, 1992
A study of single-chip processor/cache organizations for large numbers of transistors
M Farrens, G Tyson, AR Pleszkun
Proceedings of 21 International Symposium on Computer Architecture, 338-347, 1994
Improving performance of small on-chip instruction caches
MK Farrens, R Pleszkun
ACM SIGARCH Computer Architecture News 17 (3), 234-241, 1989
Address compression through base register caching
A Park, M Farrens
[1990] Proceedings of the 23rd Annual Workshop and Symposium@ m_MICRO 23 …, 1990
Cache-aware affinitization on commodity multicores for high-speed network flows
V Ahuja, M Farrens, D Ghosal
2012 ACM/IEEE Symposium on Architectures for Networking and Communications …, 2012
A comparision of superscalar and decoupled access/execute architectures
MK Farrens, P Ng, P Nico
Proceedings of the 26th annual international symposium on Microarchitecture …, 1993
Exploiting ilp in page-based intelligent memory
M Oskin, J Hensley, D Keen, FT Chong, M Farrens, A Chopra
MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999
Implementation of the pipe processor
MK Farrens, AR Pleszhun
Computer 24 (1), 65-70, 1991
Resilient microring resonator based photonic networks
CJ Nitta, MK Farrens, V Akella
2011 44th Annual IEEE/ACM International Symposium on Microarchitecture …, 2011
Exploiting superword-level locality in multimedia extension architectures
J Shin, J Chame, MW Hall
J. Instr. Level Parallel 5, 1-28, 2003
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