Anant Agarwal
Anant Agarwal
Founder and CEO of edX, Professor of Electrical Engineering and Computer Science at MIT
Verified email at - Homepage
Cited by
Cited by
The raw microprocessor: A computational fabric for software circuits and general-purpose programs
MB Taylor, J Kim, J Miller, D Wentzlaff, F Ghodrat, B Greenwald, ...
IEEE micro 22 (2), 25-35, 2002
On-chip interconnection architecture of the tile processor
D Wentzlaff, P Griffin, H Hoffmann, L Bao, B Edwards, C Ramey, ...
IEEE micro 27 (5), 15-31, 2007
Baring it all to software: Raw machines
E Waingold, M Taylor, D Srikrishna, V Sarkar, W Lee, V Lee, J Kim, ...
Computer 30 (9), 86-93, 1997
An evaluation of directory schemes for cache coherence
A Agarwal, R Simoni, J Hennessy, M Horowitz
ACM SIGARCH Computer Architecture News 16 (2), 280-298, 1988
Limits on interconnection network performance
A Agarwal
IEEE Transactions on Parallel and Distributed Systems 2 (4), 398-412, 1991
APRIL: A processor architecture for multiprocessing
A Agarwal, BH Lim, D Kranz, J Kubiatowicz
Proceedings of the 17th annual international symposium on Computer …, 1990
The MIT Alewife machine: Architecture and performance
A Agarwal, R Bianchini, D Chaiken, KL Johnson, D Kranz, J Kubiatowicz, ...
ACM SIGARCH Computer Architecture News 23 (2), 2-13, 1995
DSENT-a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling
C Sun, CHO Chen, G Kurian, L Wei, J Miller, A Agarwal, LS Peh, ...
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 201-210, 2012
Graphite: A distributed parallel simulator for multicores
JE Miller, H Kasture, G Kurian, C Gruenwald, N Beckmann, C Celio, ...
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams
MB Taylor, W Lee, J Miller, D Wentzlaff, I Bratt, B Greenwald, H Hoffmann, ...
ACM SIGARCH Computer Architecture News 32 (2), 2, 2004
LimitLESS directories: A scalable cache coherence scheme
D Chaiken, J Kubiatowicz, A Agarwal
ACM SIGARCH Computer Architecture News 19 (2), 224-234, 1991
An analytical cache model
A Agarwal, J Hennessy, M Horowitz
ACM Transactions on Computer Systems (TOCS) 7 (2), 184-215, 1989
Factored operating systems (fos) the case for a scalable operating system for multicores
D Wentzlaff, A Agarwal
ACM SIGOPS Operating Systems Review 43 (2), 76-85, 2009
Directory-based cache coherence in large-scale multiprocessors
D Chaiken, C Fields, K Kurihara, A Agarwal
Computer 23 (6), 49-58, 1990
Dynamic knobs for responsive power-aware computing
H Hoffmann, S Sidiroglou, M Carbin, S Misailovic, A Agarwal, M Rinard
ACM SIGARCH computer architecture news 39 (1), 199-212, 2011
The MIT Alewife machine: A large-scale distributed-memory multiprocessor
A Agarwal, D Chaiken, K Johnson, D Kranz, J Kubiatowicz, K Kurihara, ...
Scalable shared memory multiprocessors, 239-261, 1992
Cache performance of operating system and multiprogramming workloads
A Agarwal, J Hennessy, M Horowitz
ACM Transactions on Computer Systems (TOCS) 6 (4), 393-431, 1988
Computing in parallel processing environments
PR Griffin, M Hostetter, A Agarwal, CC Miao, CD Metcalf, B Edwards, ...
US Patent 8,738,860, 2014
Column-associative caches: A technique for reducing the miss rate of direct-mapped caches
A Agarwal, SD Pudar
Proceedings of the 20th annual international symposium on Computer …, 1993
Performance tradeoffs in multithreaded processors
A Agarwal
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