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Zhichun Zhu
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Year
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
Z Zhang, Z Zhu, X Zhang
Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000
3402000
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
H Zheng, J Lin, Z Zhang, E Gorbatov, H David, Z Zhu
2008 41st IEEE/ACM International Symposium on Microarchitecture, 210-221, 2008
3042008
A performance comparison of DRAM memory system optimizations for SMT processors
Z Zhu, Z Zhang
11th International symposium on high-performance computer architecture, 213-224, 2005
1282005
Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices
H Zheng, J Lin, Z Zhang, Z Zhu
ACM SIGARCH Computer Architecture News 37 (3), 255-266, 2009
952009
Thermal modeling and management of DRAM memory systems
J Lin, H Zheng, Z Zhu, H David, Z Zhang
Proceedings of the 34th annual international symposium on Computer …, 2007
732007
Cached DRAM for ILP processor memory access latency reduction
Z Zhang, Z Zhu, X Zhang
IEEE Micro 21 (4), 22-32, 2001
652001
Access-mode predictions for low-power cache design
Z Zhu, X Zhang
IEEE micro 22 (2), 58-71, 2002
622002
Software thermal management of DRAM memory for multicore systems
J Lin, H Zheng, Z Zhu, E Gorbatov, H David, Z Zhang
ACM SIGMETRICS Performance Evaluation Review 36 (1), 337-348, 2008
602008
Memory access scheduling schemes for systems with multi-core processors
H Zheng, J Lin, Z Zhang, Z Zhu
2008 37th International Conference on Parallel Processing, 406-413, 2008
512008
Fine-grain priority scheduling on multi-channel memory systems
Z Zhu, Z Zhang, X Zhang
Proceedings Eighth International Symposium on High Performance Computer …, 2002
482002
Power and performance trade-offs in contemporary dram system designs for multicore processors
H Zheng, Z Zhu
IEEE Transactions on Computers 59 (8), 1033-1046, 2010
452010
Memory hierarchy considerations for cost-effective cluster computing
X Du, X Zhang, Z Zhu
IEEE Transactions on Computers 49 (9), 915-933, 2000
442000
Design and optimization of large size and low overhead off-chip caches
Z Zhang, Z Zhu, X Zhang
IEEE Transactions on Computers 53 (7), 843-855, 2004
352004
Memory architecture for integrating emerging memory technologies
K Fang, L Chen, Z Zhang, Z Zhu
2011 International Conference on Parallel Architectures and Compilation …, 2011
312011
Breaking address mapping symmetry at multi-levels of memory hierarchy to reduce DRAM row-buffer conflicts
Z Zhang, Z Zhu, X Zhang
The Journal of Instruction-Level Parallelism 3, 29-63, 2001
312001
Refree: A refresh-free hybrid DRAM/PCM main memory system
B Pourshirazi, Z Zhu
2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2016
252016
Decoupled Memory Modules: Building High-Bandwidth Memory Systems from Low-Speed Dynamic Random Access Memory Devices
Z Zhu, Z Zhang, H Zheng
US Patent App. 13/145,750, 2012
222012
DRAM-level prefetching for fully-buffered DIMM: Design, performance and power saving
J Lin, H Zheng, Z Zhu, Z Zhang, H David
2007 IEEE International Symposium on Performance Analysis of Systems …, 2007
202007
Thermal modeling and management of dram systems
J Lin, H Zheng, Z Zhu, Z Zhang
IEEE Transactions on Computers 62 (10), 2069-2082, 2012
192012
Look-ahead architecture adaptation to reduce processor power consumption
Z Zhu, X Zhang
IEEE Micro 25 (4), 10-19, 2005
162005
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