Sophie Dupuis
Sophie Dupuis
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα lirmm.fr
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Παρατίθεται από
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A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans
S Dupuis, PS Ba, G Di Natale, ML Flottes, B Rouzeyre
IEEE InternationalOn-Line Testing Symposium (IOLTS), 49-54, 2014
1742014
Secure JTAG implementation using Schnorr protocol
A Das, J Da Rolt, S Ghosh, S Seys, S Dupuis, G Di Natale, ML Flottes, ...
Journal of Electronic Testing 29 (2), 193-209, 2013
322013
New testing procedure for finding insertion sites of stealthy hardware trojans
S Dupuis, PS Ba, ML Flottes, G Di Natale, B Rouzeyre
Design, Automation & Test in Europe Conference & Exhibition (DATE), 776-781, 2015
292015
Protection against hardware trojans with logic testing: Proposed solutions and challenges ahead
S Dupuis, ML Flottes, G Di Natale, B Rouzeyre
IEEE Design & Test 35 (2), 73-90, 2017
262017
On the limitations of logic testing for detecting hardware Trojans horses
ML Flottes, S Dupuis, PS Ba, B Rouzeyre
International Conference on Design & Technology of Integrated Systems in …, 2015
212015
Identification of Hardware Trojans triggering signals
S Dupuis, G Di Natale, ML Flottes, B Rouzeyre
First Workshop on Trustworthy Manufacturing and Utilization of Secure …, 2013
15*2013
Is side-channel analysis really reliable for detecting hardware Trojans?
G Di Natale, S Dupuis, B Rouzeyre
Conference on Design of Circuits and Integrated Systems (DCIS), 238-242, 2012
152012
Hardware trojan prevention using layout-level design approach
PS Ba, M Palanichamy, S Dupuis, ML Flottes, G Di Natale, B Rouzeyre
European Conference on Circuit Theory and Design (ECCTD), 1-4, 2015
142015
Stratus: A procedural circuit description language based upon Python
S Belloeil, D Dupuis, C Masson, JP Chaput, H Mehrez
International Conference on Microelectronics (ICM), 261-264, 2007
142007
Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique
PS Ba, S Dupuis, M Palanichamy, G Di Natale, B Rouzeyre
IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 254-259, 2016
112016
On the effectiveness of hardware trojan horse detection via side-channel analysis
S Dupuis, G Di Natale, ML Flottes, B Rouzeyre
Information Security Journal: A Global Perspective 22 (5-6), 226-236, 2013
112013
Logic locking: A survey of proposed methods and evaluation metrics
S Dupuis, ML Flottes
Journal of Electronic Testing 35 (3), 273-291, 2019
102019
A New Secure Stream Cipher for Scan Chain Encryption
M Da Silva, E Valea, ML Flottes, S Dupuis, G Di Natale, B Rouzeyre
IEEE International Verification and Security Workshop (IVSW), 68-73, 2018
102018
Using outliers to detect stealthy hardware trojan triggering?
PS Ba, S Dupuis, ML Flottes, G Di Natale, B Rouzeyre
IEEE International Verification and Security Workshop (IVSW), 1-6, 2016
92016
Providing confidentiality and integrity in ultra low power iot devices
E Valea, M Da Silva, ML Flottes, G Di Natale, S Dupuis, B Rouzeyre
2019 14th International Conference on Design & Technology of Integrated …, 2019
42019
SI ECCS: SECure context saving for IoT devices
E Valea, M Da Silva, G Di Natale, ML Flottes, S Dupuis, B Rouzeyre
International Conference on Design & Technology of Integrated Systems In …, 2018
42018
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths
S Belloeil-Dupuis, R Chotin-Avot, H Mehrez
Integration 46 (2), 104-118, 2013
42013
A reference low-complexity structured ASIC
L Noury, S Dupuis, N Fel
IEEE International Symposium on Circuits and Systems (ISCAS), 2709-2712, 2012
42012
Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits
M Palanichamy, PS Ba, S Dupuis, ML Flottes, G Di Natale, B Rouzeyre
Workshop on Trustworthy Manufacturing and Utilization of Secure Devices …, 2016
32016
Data path optimization using redundant arithmetic and pattern matching
S Belloeil, R Chotin-Avot, H Mehrez
Workshop on Design and Architectures (DASIP), 2007
32007
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