Alberto Sangiovanni Vincentelli
Alberto Sangiovanni Vincentelli
Professor of EECS, University of California, Berkeley
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα eecs.berkeley.edu - Αρχική σελίδα
Τίτλος
Παρατίθεται από
Παρατίθεται από
Έτος
SIS: A system for sequential circuit synthesis
EM Sentovich, KJ Singh, L Lavagno, C Moon, R Murgai, A Saldanha, ...
22821992
Logic minimization algorithms for VLSI synthesis
RK Brayton
Springer, 1984
21441984
MIS: A multiple-level logic optimization system
RK Brayton, R Rudell, A Sangiovanni-Vincentelli, AR Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1987
14961987
System-level design: Orthogonalization of concerns and platform-based design
K Keutzer, AR Newton, JM Rabaey, A Sangiovanni-Vincentelli
IEEE transactions on computer-aided design of integrated circuits and …, 2000
12682000
Hardware-software co-design of embedded systems: the POLIS approach
F Balarin, P Giusto, A Jurecska, M Chiodo, C Passerone, E Sentovich, ...
Springer Science & Business Media, 1997
10591997
Handbook of sensor networks: compact wireless and wired sensing systems
M Ilyas, I Mahgoub
CRC press, 2004
10142004
The waveform relaxation method for time-domain analysis of large scale integrated circuits
E Lelarasmee, AE Ruehli, AL Sangiovanni-Vincentelli
IEEE transactions on computer-aided design of integrated circuits and …, 1982
9361982
VIS: A system for verification and synthesis
RK Brayton, GD Hachtel, A Sangiovanni-Vincentelli, F Somenzi, A Aziz, ...
International conference on computer aided verification, 428-432, 1996
9171996
A framework for comparing models of computation
EA Lee, A Sangiovanni-Vincentelli
IEEE Transactions on computer-aided design of integrated circuits and …, 1998
8981998
Modeling cyber–physical systems
P Derler, EA Lee, AS Vincentelli
Proceedings of the IEEE 100 (1), 13-28, 2011
7862011
Design of embedded systems: Formal models, validation, and synthesis
S Edwards, L Lavagno, EA Lee, A Sangiovanni-Vincentelli
Proceedings of the IEEE 85 (3), 366-390, 1997
7571997
The TimberWolf placement and routing package
C Sechen, A Sangiovanni-Vincentelli
IEEE Journal of Solid-State Circuits 20 (2), 510-522, 1985
6681985
Logic verification using binary decision diagrams in a logic synthesis environment
S Malik, AR Wang, RK Brayton, A Sangiovanni-Vincentelli
1988 IEEE International Conference on Computer-Aided Design, 6, 7, 8, 9-6, 7 …, 1988
6661988
Metropolis: An integrated electronic system design environment
F Balarin, Y Watanabe, H Hsieh, L Lavagno, C Passerone, ...
Computer 36 (4), 45-52, 2003
6442003
Sequential circuit design using synthesis and optimization
EM Sentovich, KJ Singh, C Moon, H Savoj, RK Brayton, ...
Proceedings 1992 IEEE International Conference on Computer Design: VLSI in …, 1992
6341992
Convergence and finite-time behavior of simulated annealing
D Mitra, F Romeo, A Sangiovanni-Vincentelli
Advances in applied probability 18 (3), 747-771, 1986
6121986
Steady-state methods for simulating analog and microwave circuits
KS Kundert, JK White, AL Sangiovanni-Vincentelli
Springer Science & Business Media, 2013
5962013
Platform-based design and software design methodology for embedded systems
A Sangiovanni-Vincentelli, G Martin
IEEE Design & Test of Computers 18 (6), 23-33, 2001
5732001
Multilevel logic synthesis
RK Brayton, GD Hachtel, AL Sangiovanni-Vincentelli
Proceedings of the IEEE 78 (2), 264-300, 1990
5591990
Implicit state enumeration of finite state machines using BDD's
HJ Touati, H Savoj, B Lin, RK Brayton, A Sangiovanni-Vincentelli
1990 IEEE International Conference on Computer-Aided Design. Digest of …, 1990
5351990
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