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Dr. Naushad Alam
Dr. Naushad Alam
Department of Electronics Engineering, ZHCET, Aligarh Muslim University
Verified email at amu.ac.in - Homepage
Title
Cited by
Cited by
Year
Single-ended Schmitt-trigger-based robust low-power SRAM cell
S Ahmad, MK Gupta, N Alam, M Hasan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (8 …, 2016
1322016
Robust TFET SRAM cell for ultra-low power IoT applications
S Ahmad, N Alam, M Hasan
AEU-International Journal of Electronics and Communications 89, 70-76, 2018
602018
Low leakage fully half-select-free robust SRAM cells with BTI reliability analysis
S Ahmad, B Iqbal, N Alam, M Hasan
IEEE Transactions on Device and Materials Reliability 18 (3), 337-349, 2018
552018
Low Leakage Single Bitline 9T (SB9T) Static Random Access Memory
MH Sayeed Ahmad, M. K. Gupta, Naushad Alam
Microelectronics Journal 62, 1-11, 2017
542017
Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications
S Ahmad, N Alam, M Hasan
AEU-International Journal of Electronics and Communications 83, 366-375, 2018
482018
TFET-Based Robust 7T SRAM Cell for Low Power Applications
S Ahmad, SA Ahmad, M Muqeem, N Alam, M Hasan
IEEE Transactions on Electron Devices 66 (9), 3834 - 3840, 2019
312019
Dopingless tunnel field-effect transistor with oversized back gate: proposal and investigation
MA Raushan, N Alam, MJ Siddiqui
IEEE Transactions on Electron Devices 65 (10), 4701-4708, 2018
282018
Impact of asymmetric dual-k spacers on tunnel field effect transistors
MA Raushan, N Alam, MW Akram, MJ Siddiqui
Journal of Computational Electronics 17 (2), 756-765, 2018
192018
Carbon nanotube interconnects for low-power high-speed applications
N Alam, AK Kureshi, M Hasan, T Arslan
2009 IEEE International Symposium on Circuits and Systems, 2273-2276, 2009
182009
Multifinger MOSFETs’ optimization considering stress and INWE in static CMOS circuits
A Sharma, N Alam, S Dasgupta, A Bulusu
IEEE Transactions on Electron Devices 63 (6), 2517-2523, 2016
162016
Analysis of carbon nanotube interconnects and their comparison with Cu interconnects
N Alam, AK Kureshi, M Hasan, T Arslan
2009 International Multimedia, Signal Processing and Communication …, 2009
142009
Performance Enhancement of Junctionless Tunnel Field Effect Transistor Using Dual-k Spacers
MA Raushan, N Alam, MJ Siddiqui
Journal of Nanoelectronics and Optoelectronics 13 (6), 912-920, 2018
132018
Effective current model for inverter-transmission gate structure and its application in circuit design
A Sharma, N Alam, A Bulusu
IEEE Transactions on Electron Devices 64 (10), 4002-4010, 2017
132017
Systematic design of CNTFET based OTA and Op amp using g m/I D technique
M Yasir, N Alam
Analog Integrated Circuits and Signal Processing 102 (2), 293–307, 2020
102020
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance
N Alam, B Anand, S Dasgupta
Thirteenth International Symposium on Quality Electronic Design (ISQED), 717-722, 2012
102012
Efficient ECSM characterization considering voltage, temperature, and mechanical stress variability
B Kaur, N Alam, SK Manhas, B Anand
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (12), 3407-3415, 2014
92014
Gate-pitch optimization for circuit design using strain-engineered multifinger gate structures
N Alam, B Anand, S Dasgupta
IEEE transactions on electron devices 59 (11), 3120-3123, 2012
82012
Suppression of ambipolarity in tunnel-FETs using gate oxide as parameter: analysis and investigation
SA Ahmad, N Alam
IET Circuits, Devices & Systems 14 (3), 288-293, 2020
72020
Electrostatically doped drain junctionless transistor for low-power applications
MA Raushan, N Alam, MJ Siddiqui
Journal of Computational Electronics 18 (3), 864–871, 2019
72019
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization
B Kaur, A Sharma, N Alam, SK Manhas, B Anand
Microelectronics Journal 53, 45-55, 2016
72016
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