| Resistive memories for ultra-low-power embedded computing design E Vianello, O Thomas, G Molas, O Turkyilmaz, N Jovanović, D Garbin, ... 2014 IEEE International Electron Devices Meeting, 6.3. 1-6.3. 4, 2014 | 87 | 2014 |
| Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology P Flatresse, B Giraud, JP Noel, B Pelloux-Prayer, F Giner, DK Arora, ... 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 79 | 2013 |
| UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below L Grenouillet, M Vinet, J Gimbert, B Giraud, JP Noel, Q Liu, P Khare, ... 2012 International Electron Devices Meeting, 3.6. 1-3.6. 4, 2012 | 55 | 2012 |
| A 460 mhz at 397 mv, 2.6 ghz at 1.3 v, 32 bits vliw dsp embedding f max tracking E Beigne, A Valentian, I Miro-Panades, R Wilson, P Flatresse, F Abouzeid, ... IEEE Journal of Solid-State Circuits 50 (1), 125-136, 2014 | 54 | 2014 |
| A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAXtracking R Wilson, E Beigne, P Flatresse, A Valentian, F Abouzeid, T Benoist, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 46 | 2014 |
| Experimental investigation of 4-kb RRAM arrays programming conditions suitable for TCAM A Grossi, E Vianello, C Zambelli, P Royer, JP Noel, B Giraud, L Perniola, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018 | 34 | 2018 |
| Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs E Beigné, A Valentian, B Giraud, O Thomas, T Benoist, Y Thonnart, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 613-618, 2013 | 34 | 2013 |
| A comparative study of 6T and 4T SRAM cells in double-gate CMOS with statistical variation B Giraud, A Amara, A Vladimirescu 2007 IEEE International Symposium on Circuits and Systems, 3022-3025, 2007 | 29 | 2007 |
| Fine grain multi-VTco-integration methodology in UTBB FD-SOI technology B Pelloux-Prayer, A Valentian, B Giraud, Y Thonnart, JP Noel, P Flatresse, ... 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013 | 22 | 2013 |
| DRC2: Dynamically Reconfigurable Computing Circuit based on memory architecture KC Akyel, HP Charles, J Mottin, B Giraud, G Suraci, S Thuries, JP Noel 2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016 | 21 | 2016 |
| Technology variability from a design perspective B Nikolic, JH Park, J Kwak, B Giraud, Z Guo, LT Pang, SO Toh, R Jevtic, ... IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 1996-2009, 2011 | 20 | 2011 |
| Sneakpath compensation circuit for programming and read operations in rram-based crosspoint architectures A Levisse, B Giraud, JP Noel, M Moreau, JM Portal 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), 1-4, 2015 | 18 | 2015 |
| Self-contained integrated circuit including adjacent cells of different types J Noel, B Giraud, O Thomas US Patent 8,969,967, 2015 | 17 | 2015 |
| Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same P Flatresse, B Giraud, JP Noel, M Le Boulaire US Patent 8,482,070, 2013 | 17 | 2013 |
| SRAM voltage and current sense amplifiers in sub-32nm double-gate CMOS insensitive to process variations and transistor mismatch P Nasalski, A Makosiej, B Giraud, A Vladimirescu, A Amara 2009 IEEE International Symposium on Circuits and Systems, 3170-3173, 2009 | 15 | 2009 |
| An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch P Nasalski, A Makosiej, B Giraud, A Vladimirescu, A Amara 2008 15th IEEE International Conference on Electronics, Circuits and Systems …, 2008 | 15 | 2008 |
| Architecture, design and technology guidelines for crosspoint memories A Levisse, B Giraud, JP Noel, M Moreau, JM Portal 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2017 | 13 | 2017 |
| Design and simulation of a 128 kb embedded nonvolatile memory based on a hybrid RRAM (HfO2)/28 nm FDSOI CMOS technology JM Portal, M Bocquet, S Onkaraiah, M Moreau, H Aziza, D Deleruyelle, ... IEEE Transactions on Nanotechnology 16 (4), 677-686, 2017 | 12 | 2017 |
| Method for generating a topography of an FDSOI integrated circuit B Giraud, P Flatresse, M Le Boulaire, J Noel US Patent 9,092,590, 2015 | 12 | 2015 |
| Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation F Andrieu, R Berthelon, R Boumchedda, G Tricaud, L Brunet, P Batude, ... 2017 IEEE International Electron Devices Meeting (IEDM), 20.3. 1-20.3. 4, 2017 | 11 | 2017 |
