Victoria Caparrós Cabezas
Victoria Caparrós Cabezas
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα
Παρατίθεται από
Παρατίθεται από
Applying the Roofline Model
G Ofenbeck, R Steinmann, V Caparrós Cabezas, DG Spampinato, ...
IEEE International Symposium on Performance Analysis of Systems and Software …, 2014
Pinned to the walls—Impact of packaging and application properties on the memory and power walls
P Stanley-Marbell, VC Cabezas, RP Luijten
IEEE/ACM International Symposium on Low Power Electronics and Design, 51-56, 2011
Performance, power, and thermal analysis of low-power processors for scale-out systems
P Stanley-Marbell, VC Cabezas
2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011
DOME: towards the ASTRON & IBM center for exascale technology
PC Broekema, AJ Boonstra, VC Cabezas, T Engbersen, H Holties, ...
Proceedings of the 2012 Workshop on High-Performance Computing for Astronomy …, 2012
Extending the roofline model: Bottleneck analysis with microarchitectural constraints
VC Cabezas, M Püschel
2014 IEEE International Symposium on Workload Characterization (IISWC), 222-231, 2014
Parallelism and data movement characterization of contemporary application classes
V Caparrós Cabezas, P Stanley-Marbell
Proceedings of the twenty-third annual ACM symposium on parallelism in …, 2011
Quantitative analysis of parallelism and data movement properties across the berkeley computational motifs
VC Cabezas, P Stanley-Marbell
Proceedings of the 8th ACM international conference on Computing Frontiers, 1-2, 2011
Memory sharing by processors
VC Cabezas, R Jongerius, ML Schmatz, P Stanley-Marbell
US Patent 9,183,150, 2015
Exchanging data between memory controllers
FA Auernhammer, VC Cabezas, AC Doering, PM Sagmeister
US Patent 8,972,667, 2015
A tool for analysis and visualization of application properties
V Cabezas
Technical Report RZ3834, IBM, 2012
Device and method for exchanging data between memory controllers
FA Auernhammer, VC Cabezas, AC Doering, PM Sagmeister
US Patent App. 13/603,521, 2013
A DAG-Based Approach to Modeling Bottlenecks on Modern Microarchitectures
V Caparrós Cabezas
ETH Zurich, 2017
Synchronization Mechanism of Hardware and High-level Models for Performance Verification
V Cabezas, A Döring, H Ineichen
PARS: Parallel-Algorithmen,-Rechnerstrukturen und-Systemsoftware: Vol. 28, No. 1, 2011
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