Preeti Ranjan Panda
Preeti Ranjan Panda
Professor in Computer Science and Engineering, Indian Institute of Technology Delhi
Η διεύθυνση ηλεκτρονικού ταχυδρομείου έχει επαληθευτεί στον τομέα cse.iitd.ac.in
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Data and memory optimization techniques for embedded systems
PR Panda, F Catthoor, ND Dutt, K Danckaert, E Brockmeyer, C Kulkarni, ...
ACM Transactions on Design Automation of Electronic Systems (TODAES) 6 (2 …, 2001
5142001
Efficient utilization of scratch-pad memory in embedded processor applications
PR Panda, ND Dutt, A Nicolau
Proceedings European Design and Test Conference. ED & TC 97, 7-11, 1997
3841997
Memory issues in embedded systems-on-chip: optimizations and exploration
PR Panda, ND Dutt, A Nicolau
Springer Science & Business Media, 1999
3291999
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
PR Panda, ND Dutt, A Nicolau
ACM Transactions on Design Automation of Electronic Systems (TODAES) 5 (3 …, 2000
3102000
SystemC: a modeling platform supporting multiple design abstractions
PR Panda
Proceedings of the 14th international symposium on Systems synthesis, 75-80, 2001
2672001
Augmenting loop tiling with data alignment for improved cache performance
PR Panda, H Nakamura, ND Dutt, A Nicolau
IEEE transactions on computers 48 (2), 142-149, 1999
1461999
Power-efficient system design
PR Panda, BVN Silpa, A Shrivastava, K Gummidipudi
Springer Science & Business Media, 2010
1282010
Low-power memory mapping through reducing address bus activity
PR Panda, ND Dutt
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (3), 309-320, 1999
1051999
1995 high level synthesis design repository
PR Panda, ND Dutt
Proceedings of the 8th international symposium on System synthesis, 170-174, 1995
1031995
Local memory exploration and optimization in embedded systems
PR Panda, ND Dutt, A Nicolau
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999
991999
Architectural exploration and optimization of local memory in embedded systems
PR Panda, ND Dutt, A Nicolau
Proceedings. Tenth International Symposium on System Synthesis (Cat. No …, 1997
991997
Reducing address bus transition for low power memory mapping
PR Panda, ND Dutt
Proceedings ED&TC European Design and Test Conference, 63-68, 1996
991996
Data memory organization and optimizations in application-specific systems
PR Panda, ND Dutt, A Nicolau, F Catthoor, A Vandecappelle, ...
IEEE Design & Test of Computers 18 (3), 56-68, 2001
912001
Memory data organization for improved cache performance in embedded processor applications
PR Panda, ND Dutt, A Nicolau
ACM Transactions on Design Automation of Electronic Systems (TODAES) 2 (4 …, 1997
821997
Memory bank customization and assignment in behavioral synthesis
PR Panda
1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999
691999
Memory organization for improved data cache performance in embedded processors
P Panda, N Dutt, A Nicolau
Proceedings of 9th International Symposium on Systems Synthesis, 90-95, 1996
681996
Memory organization for improved data cache performance in embedded processors
P Panda, N Dutt, A Nicolau
Proceedings of 9th International Symposium on Systems Synthesis, 90-95, 1996
681996
Memory organization for improved data cache performance in embedded processors
PR Panda, ND Dutt, A Nicolau
Proceedings of 1996 International Symposium on System Synthesis, 90-95, 1996
681996
Exploiting off-chip memory access modes in high-level synthesis
PR Panda, ND Dutt, A Nicolau
iccad, 333-340, 1997
511997
Data cache sizing for embedded processor applications
PR Panda, ND Nicolau, A Nicolau
Proceedings Design, Automation and Test in Europe, 925-926, 1998
461998
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