Dionysios Reisis
Title
Cited by
Cited by
Year
Parallel computations on reconfigurable meshes
R Miller, VK Prasanna-Kumar, DI Reisis, QF Stout
IEEE Transactions on Computers 42 (6), 678-692, 1993
3471993
Meshes with reconfigurable buses
R Miller, VKP Kumar, D Reisis, QF Stout
Proc. 15th MIT Conference on Advance Research in VLSI, 163-178, 1988
2841988
Image computations on meshes with multiple broadcast
VK Prasanna-Kumar, D Reisis
IEEE Transactions on Pattern Analysis and Machine Intelligence 11 (11), 1194 …, 1989
991989
Image computations on reconfigurable VLSI arrays
R Miller, VK Prasanna-Kumar, DI Reisis, QF Stout
Proceedings CVPR'88: The Computer Society Conference on Computer Vision and …, 1988
751988
Conflict-free parallel memory accessing techniques for FFT architectures
D Reisis, N Vlassopoulos
IEEE Transactions on Circuits and Systems I: Regular Papers 55 (11), 3438-3447, 2008
542008
NEPHELE: An end-to-end scalable and dynamically reconfigurable optical architecture for application-aware SDN cloud data centers
P Bakopoulos, K Christodoulopoulos, G Landi, M Aziz, E Zahavi, ...
IEEE Communications Magazine 56 (2), 178-188, 2018
352018
A real-time motion estimation FPGA architecture
K Babionitakis, GA Doumenis, G Georgakarakos, G Lentaris, K Nakos, ...
Journal of Real-Time Image Processing 3 (1), 3-20, 2008
312008
An efficient multiple precision floating-point multiplier
K Manolopoulos, D Reisis, VA Chouliaras
2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011
262011
Reduced complexity superresolution for low-bitrate video compression
G Georgis, G Lentaris, D Reisis
IEEE Transactions on Circuits and Systems for Video Technology 26 (2), 332-345, 2015
222015
A real-time H. 264/AVC VLSI encoder architecture
K Babionitakis, G Doumenis, G Georgakarakos, G Lentaris, K Nakos, ...
Journal of Real-Time Image Processing 3 (1), 43-59, 2008
222008
Design and comparison of FFT VLSI architectures for SoC telecom applications with different flexibility, speed and complexity trade-offs
S Saponara, M Rovini, L Fanucci, A Karachalios, G Lentaris, D Reisis
Circuits, Systems, and Signal Processing 31 (2), 627-649, 2012
192012
An efficient convex hull computation on the reconfigurable mesh
DI Reisis
Proceedings Sixth International Parallel Processing Symposium, 142-145, 1992
191992
Efficient parallel algorithms for intermediate level vision analysis on the reconfigurable mesh
R Miller, VKP Kumar, D Reisis, Q Stout
Parallel Architectures and Algorithms for Image Understanding 185, 207, 1991
191991
Parallel Image Processing On Enhanced Arrays.
DI Reisis, VK Prasanna
ICPP, 909-912, 1987
191987
A novel architecture for efficient protocol processing in high speed communication environments
G Konstantoulakis, V Nellas, C Georgopoulos, T Orphanoudakis, ...
1st European Conference on Universal Multiservice Networks. ECUMN'2000 (Cat …, 2000
182000
Efficient implementation of the SAR sublayer and the ATM layer in high speed broadband ISDN data terminal adapters
G Doumenis, DI Reisis, GI Stassinopoulos
Proceedings of ICC'93-IEEE International Conference on Communications 1, 63-67, 1993
181993
Acceleration techniques and evaluation on multi-core CPU, GPU and FPGA for image processing and super-resolution
G Georgis, G Lentaris, D Reisis
Journal of Real-Time Image Processing 16 (4), 1207-1234, 2019
172019
Image processing on reconfigurable meshes
R Miller, VKP Kumar, D Reisis, Q Stout
From Pixels to Features II, 85-101, 1991
171991
An efficient multiple precision floating-point Multiply-Add Fused unit
K Manolopoulos, D Reisis, VA Chouliaras
Microelectronics journal 49, 10-18, 2016
162016
A personal computer hosted terminal adapter for the broadband integrated services digital network and applications
GA Doumenis, GE Konstantoulakis, DI Reisis, GI Stassinopoulos
1993 Second International Conference on Broadband Services, Systems and …, 1993
141993
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