Paul Brett
Paul Brett
Apple Inc.
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Cited by
Cited by
An analysis of performance interference effects in virtual environments
Y Koh, R Knauerhase, P Brett, M Bowman, Z Wen, C Pu
2007 IEEE International Symposium on Performance Analysis of Systems …, 2007
The 48-core scc processor: The programmer's view
TG Mattson, RF Van der Wijngaart, M Riepen, T Lehnig, P Brett, W Haas, ...
SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010
Using OS observations to improve performance in multicore systems
R Knauerhase, P Brett, B Hohlt, T Li, S Hahn
IEEE micro 28 (3), 54-66, 2008
Autonomic Computing: Concepts, Infrastructure, and Applications
A Ganek, DW Bustard, R Sterritt, KP Birman, R van Renesse, M Parashar, ...
Overview of autonomic computing: origins, evolution, direction, 1st edn. CRC …, 2006
Operating system support for overlapping-ISA heterogeneous multi-core architectures
T Li, P Brett, R Knauerhase, D Koufaty, D Reddy, S Hahn
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
Dynamic VM cloning on request from application based on mapping of virtual hardware configuration to the identified physical hardware resources
M Bowman, R Knauerhase, P Brett, R Adams
US Patent 8,336,046, 2012
Provider presence information
R Knauerhase, M Bowman, P Brett, R Adams
US Patent 7,840,636, 2010
QuickIA: Exploring heterogeneous architectures on real prototypes
N Chitlur, G Srinivasa, S Hahn, PK Gupta, D Reddy, D Koufaty, P Brett, ...
IEEE International Symposium on High-Performance Comp Architecture, 1-8, 2012
The Forgotten {ˇUncore˘}: On the {Energy-Efficiency} of Heterogeneous Cores
V Gupta, P Brett, D Koufaty, D Reddy, S Hahn, K Schwan, G Srinivasa
2012 USENIX Annual Technical Conference (USENIX ATC 12), 367-372, 2012
Hetergeneous processor apparatus and method
P Narvaez, GN Srinivasa, E Gorbatov, DR Subbareddy, M Naik, A Naveh, ...
US Patent 9,329,900, 2016
Thread migration support for architectually different cores
M Naik, GN Srinivasa, A Naveh, IM Sodhi, P Narvaez, E Gorbatov, ...
US Patent App. 13/997,811, 2014
ACCESS: Smart scheduling for asymmetric cache CMPs
X Jiang, A Mishra, L Zhao, R Iyer, Z Fang, S Srinivasan, S Makineni, ...
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
Method for booting a heterogeneous system and presenting a symmetric core view
E Weissmann, R Rappoport, M Mishaeli, H Shafi, O Lenz, JW Brandt, ...
US Patent 9,727,345, 2017
A Shared Global Event Propagation System to Enable Next Generation Distributed Services.
P Brett, RC Knauerhase, M Bowman, R Adams, A Nataraj, J Sedayao, ...
WORLDS, 2004
A1: A distributed in-memory graph database
C Buragohain, KM Risvik, P Brett, M Castro, W Cho, J Cowhig, N Gloy, ...
Proceedings of the 2020 ACM SIGMOD International Conference on Management of …, 2020
Bridging functional heterogeneity in multicore architectures
D Reddy, D Koufaty, P Brett, S Hahn
ACM SIGOPS Operating Systems Review 45 (1), 21-33, 2011
Operating system support for shared-isa asymmetric multi-core architectures
T Li, P Brett, B Hohlt, R Knauerhase, S McElderry, S Hahn
Workshop on the Interaction between Operating Systems and Computer …, 2008
Hetergeneous processor apparatus and method
P Narvaez, GN Srinivasa, E Gorbatov, DR Subbareddy, M Naik, A Naveh, ...
US Patent 9,448,829, 2016
Optimal logical processor count and type selection for a given workload based on platform thermals and power budgeting constraints
DR Subbareddy, GN Srinivasa, DA Koufaty, SD Hahn, M Naik, P Narvaez, ...
US Patent App. 13/993,547, 2014
Apparatus and method for intelligently powering heterogeneous processor components
DR Subbareddy, GN Srinivasa, E Gorbatov, SD Hahn, DA Koufaty, P Brett, ...
US Patent 9,672,046, 2017
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