Ravikumar CP

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Devanathan VaradarajanTexas Instruments Inc.Verified email at ti.com
Kamakoti VeezhinathanProfessor, Department of Computer Science, IIT MadrasVerified email at cse.iitm.ac.in
Mark M. TehranipoorIntel Charles E. Young Endowed Chair Professor, ECE, University of FloridaVerified email at ufl.edu
R GovindarajanProfessor, SERC and CSA, Indian Institute of ScienceVerified email at iisc.ac.in
Alice C ParkerDeans Professor of Electrical Engineering, University of Southern CaliforniaVerified email at usc.edu
Lalit Mohan PatnaikAdjunct Professor and NASI(National Academy of Sciences India) Senior Scientist, NIAS,BangaloreVerified email at alumni.iisc.ac.in
Ashutosh VermaSamsungVerified email at samsung.com
Vineet SahulaMNIT JaipurVerified email at mnit.ac.in
Nishit NarangVerified email at alumni.iitd.ac.in
Jim PlusquellicUniversity of New MexicoVerified email at ece.unm.edu
Vikram SaxenaMetaVerified email at fb.com
Xiaoqing WenKyushu Institute of TechnologyVerified email at cse.kyutech.ac.jp
Senthil ArasuApple IncVerified email at apple.com
Manimaran GovindarasuProfessor of Electrical and Computer Engineering, Iowa State UniversityVerified email at iastate.edu
Nitin ChandrachoodanIIT MadrasVerified email at ee.iitm.ac.in
Suhrid WadekarVerified email at princelobel.com
Suresh ChandraProfessor(Retired) of Mathematics,Indian Institute of Technology,New DelhiVerified email at maths.iitd.ac.in
Anand GoelStevens Institute of TechnologyVerified email at stevens.edu
Erik LarssonLunds UniversitetVerified email at eit.lth.se
Ramakrishna KakaralaOmnivision Technologies, IncVerified email at ieee.org

Ravikumar CP

Director of Technical Talent Development, Texas Instruments

Verified email at ti.com - Homepage

VLSI Design VLSI Testing High Performance Computing Embedded Systems


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Source-based delay-bounded multicasting in multimedia networks CP Ravikumar, R Bajpai Computer communications 21 (2), 126-132, 1998	135	1998
Source-based delay-bounded multicasting in multimedia networks CP Ravikumar, R Bajpai Computer communications 21 (2), 126-132, 1998	135	1998
At-speed transition fault testing with low speed scan enable N Ahmed, CP Ravikumar, M Tehranipoor, J Plusquellic 23rd IEEE VLSI Test Symposium (VTS'05), 42-47, 2005	77	2005
Test strategies for low power devices CP Ravikumar, M Hirech, X Wen Proceedings of the conference on Design, automation and test in Europe, 728-733, 2008	59	2008
Partial gating optimization for power reduction during test application M ElShoukry, M Tehranipoor, CP Ravikumar 14th Asian Test Symposium (ATS'05), 242-247, 2005	55	2005
Leakage power estimation for deep submicron circuits in an ASIC design environment R Kumar, CP Ravikumar Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002	55	2002
Glitch-aware pattern generation and optimization framework for power-safe scan test VR Devanathan, CP Ravikumar, V Kamakoti 25th IEEE VLSI Test Symposium (VTS'07), 167-172, 2007	52	2007
Software power optimizations in an embedded system V Dalal, CP Ravikumar VLSI Design 2001. Fourteenth International Conference on VLSI Design, 254-259, 2001	50	2001
Local at-speed scan enable generation for transition fault testing using low-cost testers N Ahmed, M Tehranipoor, CP Ravikumar, KM Butler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007	46	2007
Genetic algorithm for mapping tasks onto a reconfigurable parallel processor CP Ravikumar, AK Gupta IEE Proceedings-Computers and Digital Techniques 142 (2), 81-86, 1995	45	1995
Simultaneous module selection and scheduling for power-constrained testing of core based systems CP Ravikumar, G Chandra, A Verma VLSI Design 2000. Wireless and Digital Imaging in the Millennium …, 2000	37	2000
A polynomial-time algorithm for power constrained testing of core based systems CP Ravikumar, A Verma, G Chandra Proceedings Eighth Asian Test Symposium (ATS'99), 107-112, 1999	37	1999
Fast, layout-aware validation of test-vectors for nanometer-related timing failures A Kokrady, CP Ravikumar 17th International Conference on VLSI Design. Proceedings., 597-602, 2004	35	2004
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test VR Devanathan, CP Ravikumar, V Kamakoti 2007 IEEE International Test Conference, 1-10, 2007	33	2007
On power-profiling and pattern generation for power-safe scan tests VR Devanathan, CP Ravikumar, V Kamakoti 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007	33	2007
Enhanced launch-off-capture transition fault testing N Ahmed, M Tehranipoor, CP Ravikumar IEEE International Conference on Test, 2005., 10 pp.-255, 2005	32	2005
Static verification of test vectors for IR drop failure AA Kokrady, CP Ravikumar ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003	31	2003
PMScan: A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test VR Devanathan, CP Ravikumar, R Mehrotra, V Kamakoti 2007 IEEE International Test Conference, 1-9, 2007	30	2007
Multiprocessor architectures for embedded system-on-chip applications CP Ravikumar 17th International Conference on VLSI Design. Proceedings., 512-519, 2004	30	2004
A critical-path-aware partial gating approach for test power reduction M Elshoukry, M Tehranipoor, CP Ravikumar ACM Transactions on Design Automation of Electronic Systems (TODAES) 12 (2 …, 2007	28	2007

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